Document Outline

COVER
Major Revisions in This Edition
INTRODUCTION
CHAPTER 1 OUTLINE
- 1.1 Features
- 1.2 Applications
- 1.3 Ordering Information
- 1.4 Quality Grade
- 1.5 Pin Configuration (Top View)
- 1.6 78K/0 Series Lineup
- 1.7 Block Diagram
- 1.8 Overview of Functions
- 1.9 Mask Options
CHAPTER 2 PIN FUNCTIONS
- 2.1 Pin Function List
  - 2.1.1 Normal operating mode pins
  - 2.1.2 PROM programming mode pins (uPD78P0208 only)
- 2.2 Description of Pin Functions
  - 2.2.1 P00 to P04 (Port 0)
  - 2.2.2 P10 to P17 (Port 1)
  - 2.2.3 P20 to P27 (Port 2)
  - 2.2.4 P30 to P37 (Port 3)
  - 2.2.5 P70 to P74 (Port 7)
  - 2.2.6 P80 to P87 (Port 8)
  - 2.2.7 P90 to P97 (Port 9)
  - 2.2.8 P100 to P107 (Port 10)
  - 2.2.9 P110 to P117 (Port 11)
  - 2.2.10 P120 to P127 (Port 12)
  - 2.2.11 FIP0 to FIP12
  - 2.2.12 VLOAD
  - 2.2.13 AVREF
  - 2.2.14 AVDD
  - 2.2.15 AVSS
  - 2.2.16 RESET#
  - 2.2.17 X1 and X2
  - 2.2.18 XT1 and XT2
  - 2.2.19 VDD
  - 2.2.20 VSS
  - 2.2.21 VPP (uPD78P0208 only)
  - 2.2.22 IC (mask ROM version only)
- 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
CHAPTER 3 CPU ARCHITECTURE
- 3.1 Memory Space
  - 3.1.1 Internal program memory space
  - 3.1.2 Internal data memory space
  - 3.1.3 Special-function register (SFR) area
  - 3.1.4 Data memory addressing
- 3.2 Processor Registers
  - 3.2.1 Control registers
  - 3.2.2 General-purpose registers
  - 3.2.3 Special-function registers (SFRs)
- 3.3 Instruction Address Addressing
  - 3.3.1 Relative addressing
  - 3.3.2 Immediate addressing
  - 3.3.3 Table indirect addressing
  - 3.3.4 Register addressing
- 3.4 Operand Address Addressing
  - 3.4.1 Implied addressing
  - 3.4.2 Register addressing
  - 3.4.3 Direct addressing
  - 3.4.4 Short direct addressing
  - 3.4.5 Special-function register (SFR) addressing
  - 3.4.6 Register indirect addressing
  - 3.4.7 Based addressing
  - 3.4.8 Based indexed addressing
  - 3.4.9 Stack addressing
CHAPTER 4 PORT FUNCTIONS
- 4.1 Port Functions
- 4.2 Port Configuration
  - 4.2.1 Port 0
  - 4.2.2 Port 1
  - 4.2.3 Port 2
  - 4.2.4 Port 3
  - 4.2.5 Port 7
  - 4.2.6 Port 8
  - 4.2.7 Port 9
  - 4.2.8 Port 10
  - 4.2.9 Port 11
  - 4.2.10 Port 12
- 4.3 Port Function Control Registers
- 4.4 Port Function Operations
  - 4.4.1 Writing to I/O port
  - 4.4.2 Reading from I/O port
  - 4.4.3 Operations on I/O port
- 4.5 Selection of Mask Option
CHAPTER 5 CLOCK GENERATOR
- 5.1 Clock Generator Functions
- 5.2 Clock Generator Configuration
- 5.3 Clock Generator Control Registers
- 5.4 System Clock Oscillator
  - 5.4.1 Main system clock oscillator
  - 5.4.2 Subsystem clock oscillator
  - 5.4.3 Divider
  - 5.4.4 When subsystem clock is not used
- 5.5 Clock Generator Operations
  - 5.5.1 Main system clock operations
  - 5.5.2 Subsystem clock operations
- 5.6 Changing System Clock and CPU Clock Settings
  - 5.6.1 Time required for switchover between system clock and CPU clock
  - 5.6.2 System clock and CPU clock switching procedure
CHAPTER 6 16-BIT TIMER/EVENT COUNTER
- 6.1 Outline of Timers Incorporated in uPD780208 Subseries
- 6.2 16-Bit Timer/Event Counter Functions
- 6.3 16-Bit Timer/Event Counter Configuration
- 6.4 16-Bit Timer/Event Counter Control Registers
- 6.5 16-Bit Timer/Event Counter Operations
  - 6.5.1 Interval timer operations
  - 6.5.2 PWM output operations
  - 6.5.3 Pulse width measurement operations
  - 6.5.4 External event counter operation
  - 6.5.5 Square-wave output operation
- 6.6 16-Bit Timer/Event Counter Operating Precautions
CHAPTER 7 8-BIT TIMER/EVENT COUNTER
- 7.1 8-Bit Timer/Event Counter Functions
  - 7.1.1 8-bit timer/event counter mode
  - 7.1.2 16-bit timer/event counter mode
- 7.2 8-Bit Timer/Event Counter Configuration
- 7.3 8-Bit Timer/Event Counter Control Registers
- 7.4 8-Bit Timer/Event Counter Operations
  - 7.4.1 8-bit timer/event counter mode
  - 7.4.2 16-bit timer/event counter mode
- 7.5 8-Bit Timer/Event Counter Operating Precautions
CHAPTER 8 WATCH TIMER
- 8.1 Watch Timer Functions
- 8.2 Watch Timer Configuration
- 8.3 Watch Timer Control Registers
- 8.4 Watch Timer Operations
  - 8.4.1 Watch timer operation
  - 8.4.2 Interval timer operation
CHAPTER 9 WATCHDOG TIMER
- 9.1 Watchdog Timer Functions
- 9.2 Watchdog Timer Configuration
- 9.3 Watchdog Timer Control Registers
- 9.4 Watchdog Timer Operations
  - 9.4.1 Watchdog timer operation
  - 9.4.2 Interval timer operation
CHAPTER 10 CLOCK OUTPUT CONTROLLER
- 10.1 Clock Output Controller Functions
- 10.2 Clock Output Controller Configuration
- 10.3 Clock Output Function Control Registers
CHAPTER 11 BUZZER OUTPUT CONTROLLER
- 11.1 Buzzer Output Controller Functions
- 11.2 Buzzer Output Controller Configuration
- 11.3 Buzzer Output Function Control Registers
CHAPTER 12 A/D CONVERTER
- 12.1 A/D Converter Functions
- 12.2 A/D Converter Configuration
- 12.3 A/D Converter Control Registers
- 12.4 A/D Converter Operations
  - 12.4.1 Basic operations of A/D converter
  - 12.4.2 Input voltage and conversion results
  - 12.4.3 A/D converter operating mode
- 12.5 A/D Converter Precautions
CHAPTER 13 SERIAL INTERFACE CHANNEL 0
- 13.1 Functions of Serial Interface Channel 0
- 13.2 Configuration of Serial Interface Channel 0
- 13.3 Control Registers of Serial Interface Channel 0
- 13.4 Operations of Serial Interface Channel 0
  - 13.4.1 Operation stop mode
  - 13.4.2 3-wire serial I/O mode operation
  - 13.4.3 SBI mode operation
  - 13.4.4 2-wire serial I/O mode operation
  - 13.4.5 SCK0#/P27 pin output manipulation
CHAPTER 14 SERIAL INTERFACE CHANNEL 1
- 14.1 Functions of Serial Interface Channel 1
- 14.2 Configuration of Serial Interface Channel 1
- 14.3 Control Registers of Serial Interface Channel 1
- 14.4 Operations of Serial Interface Channel 1
  - 14.4.1 Operation stop mode
  - 14.4.2 3-wire serial I/O mode operation
  - 14.4.3 3-wire serial I/O mode operation with automatic transmit/receive function
CHAPTER 15 VFD CONTROLLER/DRIVER
- 15.1 VFD Controller/Driver Functions
- 15.2 VFD Controller/Driver Configuration
- 15.3 VFD Controller/Driver Control Registers
  - 15.3.1 Control registers
  - 15.3.2 One-display period and cut width
- 15.4 Selecting Display Mode
- 15.5 Display Mode and Display Output
- 15.6 Display Data Memory
- 15.7 Key Scan Flag and Key Scan Data
  - 15.7.1 Key scan flag
  - 15.7.2 Key scan data
- 15.8 Light Leakage of VFD
- 15.9 Display Examples
  - 15.9.1 Segment type (display mode 1: DSPM05 = 0)
  - 15.9.2 Dot type (display mode 1: DSPM05 = 0)
  - 15.9.3 Display type in which a segment spans two or more grids (display mode 2: DSPM05 = 1)
- 15.10 Calculating Total Power Dissipation
  - 15.10.1 Segment type (display mode 1: DSPM05 = 0)
  - 15.10.2 Dot type (display mode 1: DSPM05 = 0)
  - 15.10.3 Display type in which a segment spans two or more grids (display mode 2: DSPM05 = 1)
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS
- 16.1 Interrupt Function Types
- 16.2 Interrupt Sources and Configuration
- 16.3 Interrupt Function Control Registers
- 16.4 Interrupt Servicing Operations
  - 16.4.1 Non-maskable interrupt request acknowledgment operation
  - 16.4.2 Maskable interrupt request acknowledgment operation
  - 16.4.3 Software interrupt request acknowledgment operation
  - 16.4.4 Multiple interrupt servicing
  - 16.4.5 Interrupt request hold
- 16.5 Test Functions
  - 16.5.1 Test function control registers
  - 16.5.2 Test input signal acknowledgment operation
CHAPTER 17 STANDBY FUNCTION
- 17.1 Standby Function and Configuration
  - 17.1.1 Standby function
  - 17.1.2 Standby function control register
- 17.2 Standby Function Operations
  - 17.2.1 HALT mode
  - 17.2.2 STOP mode
CHAPTER 18 RESET FUNCTION
- 18.1 Reset Function
CHAPTER 19 uPD78P0208
- 19.1 Internal Memory Size Switching Register
- 19.2 Internal Expansion RAM Size Switching Register
- 19.3 PROM Programming
  - 19.3.1 Operating modes
  - 19.3.2 PROM write procedure
  - 19.3.3 PROM read procedure
- 19.4 Screening of One-Time PROM Version
CHAPTER 20 INSTRUCTION SET
- 20.1 Conventions
  - 20.1.1 Operand identifiers and description methods
  - 20.1.2 Description of operationŽ column
  - 20.1.3 Description of flag operationŽ column
- 20.2 Operation List
- 20.3 Instructions Listed by Addressing Type
APPENDIX A DIFFERENCES BETWEEN uPD78044H, 780228, AND 780208 SUBSERIES
APPENDIX B DEVELOPMENT TOOLS
- B.1 Software Package
- B.2 Language Processing Software
- B.3 Control Software
- B.4 PROM Programming Tools
  - B.4.1 Hardware
  - B.4.2 Software
- B.5 Debugging Tools (Hardware)
  - B.5.1 When using in-circuit emulator IE-78K0-NS, IE-78K0-NS-A
  - B.5.2 When using in-circuit emulator IE-78001-R-A
- B.6 Debugging Tools (Software)
- B.7 Embedded Software
- B.8 Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A
- B.9 Conversion Socket (EV-9200GF-100) Package Drawing and Recommended Footprint
- B.10 Notes on Target System Design
APPENDIX C REGISTER INDEX
- C.1 Register Index (by Register Name)
- C.2 Register Index (by Register Symbol)
APPENDIX D REVISION HISTORY

User's Manual U11302EJ4V0UM

FIP and IEBus are trademarks of NEC Electronics Corporation.

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in the United States and/or other countries.

IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.

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TRON stands for The Realtime Operating system Nucleus.

ITRON is an abbreviation of Industrial TRON.

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

User's Manual U11302EJ4V0UM

The information in this document is current as of January, 2003. The information is subject to
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M8E 02. 11-1

These commodities, technology or software, must be exported in accordance
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Diversion contrary to the law of that country is prohibited.

User's Manual U11302EJ4V0UM

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Document Outline

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